The present invention relates generally to integrated circuits and, more particularly, to a seal ring structure for integrated circuits.
In the design and packaging of integrated circuits, moisture needs to be prevented from entering the circuits for a variety of reasons. Moisture can be trapped in oxides and increase the dielectric constant thereof, which affects, for example, the MIM capacitors, gate oxide capacitors, and parasitic interconnect capacitors. Moisture can also create trapped charge centers in gate oxides causing threshold voltage shifts in MOS transistors. Additionally, moisture can create interface states at the Si-gate oxide interface causing degradation in the transistor lifetime through increased hot-electron susceptibility. Moisture also can cause corrosion of the metal interconnect, reducing the reliability of the integrated circuit (IC). When trapped in Si-oxide, moisture reduces the oxide mechanical strength and the oxide becomes more prone to cracking due to tensile stress.
Ionic contaminants can also cause damage to the IC as they can diffuse rapidly in silicon oxide. For instance, ionic contaminants can cause threshold voltage instability in the CMOS transistors, and alter the surface potential of the Si surface in the vicinity of the ionic contaminants.
A seal ring is typically used to protect the IC from moisture degradation and ionic contamination. One conventional seal ring design is illustrated in FIGS. 1a and 1b. The seal ring 8 comprises a stack of metal/contact/via layers 10 (including metal M1-M6, vias V1-V5, contact Co, and intermetal oxide IMO0-IM05) disposed on the die 12 and connected to the silicon substrate 14 (FIG. 1a). At the top are a passivation oxide layer 16 and a passivation nitride layer 18. Below the contact Co are salicide 22 and P+ region 24 disposed adjacent a shallow trench isolation (STI) 26. The seal ring 8 provides a boundary around the entire IC chip 12 (FIG. 1b). This boundary forms an impervious wall around the IC circuits in the die 12, preventing moisture and ionic contamination from penetrating the IC 12.
The seal ring 8 has been shown to provide good protection to the circuit inside the die 12, and is widely used in the industry for integrated circuits. As seen in FIGS. 1a and 1b, the seal ring 8 electrically connects all round the die periphery. This electrical connection does not cause problems for digital circuits. Analog and RF circuits, however, are susceptible to low noise voltages. Efforts are made in the design of such circuits to prevent noise coupling from one circuit element to another. In an IC where there are digital circuits and RF/analog circuits integrated on the same Si-substrate, noise coupling prevention becomes a greater challenge. The digital circuits generate a substantial amount of noise and some of it is coupled to the substrate and can propagate through the substrate to other parts of the die. To reduce the impact of this on specially sensitive circuits, a common practice is to keep such sensitive circuits physically distant from the noisy digital circuits, while using a high resistivity substrate. The seal ring 8, however, electrically connects the periphery of the circuit 12 through a low resistance metal interconnect (M1-M6), as seen from FIGS. 1a and 1b. As a result of the presence of the conventional seal ring 8, circuits which were designed to be physically and electrically distant are brought electrically close to one other and allow coupling of noise between the circuit.
Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate. In this way, the seal ring provides substantially reduced noise coupling among the circuits but still maintains an effective wall around the periphery of the die to protect the circuits against moisture and ionic contamination penetration.
In accordance with an aspect of the present invention, an integrated circuit comprises a digital circuit and at least one of an analog circuit and an RF circuit in an integrated circuit die. A seal ring is disposed around the integrated circuit die. The seal ring includes at least one cut between a portion of the seal ring which is disposed adjacent to the digital circuit and another portion of the seal ring which is disposed adjacent to the at least one of an analog circuit and an RF circuit.
In some embodiments, the seal ring includes a plurality of cuts separating the seal ring into a plurality of seal ring portions disposed adjacent to different circuits in the integrated circuit die. The cut is about 0.3 xcexcm to about 5 xcexcm in width, and is typically about 1 xcexcm in width. In specific embodiments, the seal ring comprises a metal stack disposed on a substrate along a boundary of the integrated circuit die, and the cut extends through the metal stack.
The seal ring desirably is at least substantially isolated electrically from the substrate of the integrated circuit die. In specific embodiments, the metal stack is separated from the substrate by a polysilicon layer. A gate oxide is formed between the polysilicon layer and the substrate. The gate oxide has a thickness of about 20 to about 100 angstroms. The substrate is a p-type substrate and an n-well is formed between the gate oxide and the p-type substrate.
In accordance with another aspect of the invention, an integrated circuit comprises a digital circuit and at least one of an analog circuit and an RF circuit in an integrated circuit die which includes a substrate. A seal ring is disposed on the substrate along a boundary of the integrated circuit die. The seal ring is at least substantially isolated electrically from the substrate of the integrated circuit die for reduction of noise coupling therebetween.
In some embodiments, the seal ring is separated from the substrate by a polysilicon layer and a gate oxide. An n-well/p-well capacitor is formed in the substrate in series with the gate oxide. The seal ring may include at least one cut between a portion of the seal ring which is disposed adjacent to the digital circuit and another portion of the seal ring which is disposed adjacent to the at least one of an analog circuit and an RF circuit.
Another aspect of the present invention is directed to a method of reducing noise coupling by a seal ring between a digital circuit and at least one of an analog circuit and an RF circuit in an integrated circuit die. The method includes forming a seal ring on a substrate of the integrated circuit die along a boundary of the integrated circuit die, and providing at least one cut in the seal ring to separate the seal ring into a plurality of seal ring portions which are disposed adjacent to different circuits in the integrated circuit die.
In some embodiments, the method includes providing a capacitance having a sufficiently large impedance between the seal ring and the substrate to reduce coupling of low frequency noise generated by the digital circuit therebetween. It may include forming a polysilicon layer and a gate oxide between the seal ring and the substrate. It may further include forming an n-well/p-well capacitor in the substrate in series with a gate oxide capacitor produced by the gate oxide. In specific embodiments, the n-well/p-well capacitor is formed by providing a p-type substrate and forming an n-well between the p-type substrate and the gate oxide.